1. Field of the Invention
The present invention relates to a picture coding apparatus and, more specifically, to a picture coding apparatus which compresses moving pictures or still pictures to less than a predetermined code amount.
2. Description of the Prior Art
FIG. 11 shows the configuration of a conventional picture coding apparatus. In this apparatus, a frame picture is divided into non-overlapping blocks of (8 pixels).times.(8 lines) and variable-length coding is performed by orthogonal-transforming each block while a control is so made that the one-frame code amount falls within a target code amount. As for the orthogonal transform, the two-dimensional discrete cosine transform (DCT) is generally used.
Referring to FIG. 11, a digital video input signal is input to a block conversion circuit 61 via an input terminal 1. The block conversion circuit 61 writes the signal into an internal memory (not shown) in the field order, and outputs a one-frame signal to a DCT circuit 3 on an 8-pixel/8-line block basis by properly controlling the memory once the one-frame signal is stored in the memory.
The DCT circuit 3 DCT-transforms the signal of an 8-pixel/8-line block basis that is supplied from the block transform circuit 61, and outputs resulting DCT coefficients to a frame memory 76 and four quantization circuits 62-65.
The four quantization circuits quantize the DCT coefficients by using respective quantization tables 66-69 and different quantization steps, and output quantized coefficients to respective variable-length code amount accumulation circuits 70-73.
Each of the variable-length code amount accumulation circuits 70-73 accumulates the corresponding set of quantized coefficients, i.e., the code amount of the variable-length coding over one frame, and outputs an accumulated code amount to a quantization characteristic function calculation circuit 74.
The quantization characteristic function calculation circuit 74 calculates a code amount characteristic function indicating the characteristic of an input picture based on two sets of an accumulated code amount and a quantization step in which the two accumulated code amounts are closest to the target code amount, and outputs the calculated function to a quantization step calculation circuit 75.
The quantization step calculating circuit 75 predicts, by using the code amount characteristic function, a quantization step which would make the code amount smaller than the target code amount, and outputs the predicted quantization step to a quantization circuit 9 which is used for actual quantization.
The quantization circuit 9 quantizes DCT coefficients as delayed by a frame memory 76 by using a quantization table 13 and the received quantization step, and outputs quantized coefficients to a variable-length coding circuit (VLC circuit) 11.
The VLC circuit 11 performs variable-length coding such as run-length coding and/or Huffman coding, and outputs coded data.
An example of the above picture coding scheme is described in detail in M. Enari and M. Kashida, "`HDTV codec` for 60-140 Mbps," Video Information, January 1992, pp. 51-58.
In the above-described conventional picture coding apparatus, control is so made as to code a one-frame picture to produce a code amount that is smaller than the target code amount by analyzing one-frame data by means of a plurality of quantizers and code amount accumulation circuits.
However, because 4 to 8 quantizers and variable-length code amount accumulation circuits need to be operated in parallel to obtain reproduction of high quality picture, the above conventional scheme is disadvantageous in that not only the circuit scale is increased but also an input picture needs to be delayed for a data analyzing period during which the quantization, the code amount accumulation, and the quantization step prediction are performed. Thus, the conventional scheme has a problem that it is very difficult to reduce the power consumption, size, and weight.